- 2.1 - Basics of MOS Transistor: Introduction to MOSFET
- 2.2 - Basics of MOS Transistor: Gate Voltage & Accumulation of Negative Charge
- 2.3 - Basics of MOS Transistor: NChannel Formation Between Source & Drain
- 2.4 - Basics of MOS Transistor: Impact Of Substrate Potential On threshold Voltage
- 2.5 - Basics of MOS Transistor: Threshold voltage with body complete
- 2.6 - Basics of MOS Transistor: Exercise 1
- 2.7 - Basics of MOS Transistor: Excercise 2
- 3.1 - SpecificationsToCHIP
- 3.2 - Chip Dimension And Intro To Preplaced Cells
- 3.3 - Pre Placed Cells Concluded
- 3.4 - Decoupling Capacitors And Power Plan
- 3.5 - Example For Netlist And Pin Placement
- 3.6 - Pin Placement And Intro To PNR
- 3.7 - Example Continued For PNR
- 3.8 - Placement And Optimize Placement
- 3.9 - Optimize Placement Continued
- 3.10 - Optimize Placement Concluded
- 3.11 - STA ideal clocks
- 3.12 - STA ideal clocks with Setup Time
- 3.13 - STA ideal clocks with Example
- 3.14 - STA ideal multiple clocks
- 3.15 - STA ideal multiple clocks with example
- 3.16 - STA Data slew check
- 3.17 - STA Data slew check example
- 3.18 - ClockTreeSyntehsis HTree
- 4.1 - Introduction to Clock Tree
- 4.2 - Skew Pulse Width Quality Checks
- 4.3 - Duty Cycle Latency Quality Checks
- 4.4 - Latenct Power Quality Check
- 4.5 - Power Quality Check
- 4.6 - Power Crosstalk Quality Check
- 4.7 - Delta Delay Quality Check
- 4.8 - Glitch Quality Check
- 5.1 - HTree Skew Check
- 5.2 - HTree Pulse Width Duty Cycle Check
- 5.3 - Htree Latency Power Check
- 6.1 - Clock tree Modelling
- 6.2 - Clock Tree Buffering
- 6.3 - Clock Tree Building
- 6.4 - Clock Tree Observations
- 7.1 - HTree Buffering Observations
- 7.2 - HTree Skew Check
- 7.3 - HTree Pulse Width Check Regular And Clock Buffer
- 7.4 - Inverter Resistance Difference
- 7.5 - Inverter Resistance Match Solution
- 7.6 - HTree CBUF Pulse Width Check MET
- 7.7 - Duty Cycle Latency Power check Intro
- 7.8 - Dynamic Short Circuit Power Revisited
- 7.9 - Leakage Power Revisit
- 8.1 - Optimization CheckList
- 8.2 - Short Circuit current Revisited
- 8.3 - Leakage Current Revisited
- 8.4 - Clock Tree Optimized
- 8.5 - Optimized Clock Tree Power Latency Check
- 9.1 - Clock Tree Uneven Clk End Points Spread
- 9.2 - Logical To Physical Connection
- 9.3 - Uneven clock Endpoints HTree CheckList
- 9.4 - Advanced HTree Million Flops
- 10.1 - Power Aware CTS Intro To Gates
- 10.2 - Delay Table Usage 1
- 10.3 - Delay Table Usage 2
- 10.4 - Clock Gating Using AND Gate and Skew Cal
- 10.5 - Skew Issue Solution
- 10.6 - OR AND simultaneous clock gating technique
- 10.7 - NAND gates as clock gating cells
- 10.8 - Clock Gating Technique on Real Chip
- 11.1 - Setup timing Analysis Real Clocks
- 11.2 - Intro To Data Arrival And Required Time
- 11.3 - Setup Timing Degrade by unbalanced Skew
- 11.4 - Hold Timing Analysis Real Clocks
- 11.5 - Hold Timing Degrade by unbalanced Skew
- 11.6 - Summary
- Mega QUIZ
the depletion region will form to a certain extent after that negative charges will be attracted towards gate from n+ substrate to compensate the positive voltage from gate.
answered by saichaitanya, 3 months ago. [ 2nd - Jul, 2017 ]
A flip-flop is a binary storage device.It can store one bit of information. It is an edge triggered device as it works only when clock is having transition from high level to low level or vice versa.
answered by NAVNEETKISHAN, [ Jul, 2016 ]
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